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d a t a sh eet product speci?cation 2003 sep 30 discrete semiconductors BF1205 dual n-channel dual gate mos-fet a ndbook, halfpage mbd128
2003 sep 30 2 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 features two low noise gain controlled amplifiers in a single package. one with a fully integrated bias and one with a partly integrated bias internal switch reduces the number of external components superior cross-modulation performance during agc high forward transfer admittance high forward transfer admittance to input capacitance ratio. applications gain controlled low noise amplifiers for vhf and uhf applications with 5 v supply voltage, such as digital and analog television tuners and professional communications equipment. description the BF1205 is a combination of two equal dual gate mos-fet amplifiers with shared source and gate 2 leads and an integrated switch. the integrated switch is operated by the gate 1 bias of amplifier b. the source and substrate are interconnected. internal bias circuits enable dc stabilization and a very good cross-modulation performance during agc. integrated diodes between the gates and source protect against excessive input voltage surges. the transistor is encapsulated in sot363 micro-miniature plastic package. pinning - sot363 pin description 1 gate 1 (a) 2 gate 2 3 gate 1 (b) 4 drain (b) 5 source 6 drain (a) handbook, halfpage 123 654 top view mgx429 amp a d (a) s d (b) g1 (a) g2 g1 (b) amp b fig.1 simplified outline and symbol. marking code: l4-. ordering information type number package name description version BF1205 - plastic surface mounted package; 6 leads sot363
2003 sep 30 3 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 quick reference data limiting values in accordance with the absolute maximum rating system (iec 60134). note 1. t s is the temperature at the soldering point of the source lead. thermal characteristics symbol parameter conditions min. typ. max. unit per mos-fet; unless otherwise speci?ed v ds drain-source voltage -- 10 v i d drain current (dc) -- 30 ma p tot total power dissipation t s 102 c; temperature at the soldering point of the source lead -- 200 mw ? y fs ? forward transfer admittance i d =12ma 263140 ms c ig1-ss input capacitance at gate 1 amp. a: f = 1 mhz - 1.8 2.3 pf amp. b: f = 1 mhz - 2.0 2.5 pf c rss reverse transfer capacitance f = 1 mhz - 20 - ff nf noise ?gure amp. a: f = 800 mhz - 1.2 1.9 db amp. b: f = 800 mhz - 1.4 2.1 db x mod cross-modulation amp. a: input level for k = 1% at 40 db agc 98 102 - db m v amp. b: input level for k = 1% at 40 db agc 100 105 - db m v t j junction temperature -- 150 c caution this product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. for further information, refer to philips specs.: snw-eq-608, snw-fq-302a and snw-fq-302b. symbol parameter conditions min. max. unit per mos-fet; unless otherwise speci?ed v ds drain-source voltage - 10 v i d drain current (dc) - 30 ma i g1 gate 1 current - 10 ma i g2 gate 2 current - 10 ma p tot total power dissipation t s 102 c; note - 200 mw t stg storage temperature - 65 +150 c t j junction temperature - 150 c symbol parameter value unit r th j-s thermal resistance from junction to soldering point 240 k/w
2003 sep 30 4 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 0 50 100 200 250 0 200 mgs359 150 150 100 50 t s ( c) p tot (mw) fig.2 power derating curve. static characteristics t j =25 c; per mos-fet; unless otherwise speci?ed. note 1. r g1 connects gate 1 (b) to v gg = 0 v (see fig.4). 2. r g1 connects gate 1 (b) to v gg = 5 v (see fig.4). symbol parameter conditions min. max. unit v (br)dss drain-source breakdown voltage amp. a: v g1-s =v g2-s =0v; i d =10 m a10 - v amp. b: v g1-s =v g2-s =0v; i d =10 m a7 - v v (br)g1-ss gate-source breakdown voltage v gs =v ds =0v; i g1-s = 10 ma 6 10 v v (br)g2-ss gate-source breakdown voltage v gs =v ds =0v; i g2-s = 10 ma 6 10 v v (f)s-g1 forward source-gate voltage v g2-s =v ds =0v; i s-g1 = 10 ma 0.5 1.5 v v (f)s-g2 forward source-gate voltage v g1-s =v ds =0v; i s-g2 = 10 ma 0.5 1.5 v v g1-s(th) gate-source threshold voltage v ds =5v; v g2-s =4v; i d = 100 m a 0.3 1 v v g2-s(th) gate-source threshold voltage v ds =5v; v g1-s =5v; i d = 100 m a 0.4 1.0 v i dsx drain-source current amp. a: v g2-s =4v; v ds =5v; r g1 = 150 k w ; note 1 816ma amp. b: v g2-s =4v; v ds =5v; r g1 = 150 k w ; note 2 816ma i g1-s gate cut-off current amp. a: v g1-s =5v; v g2-s =v ds =0v - 50 na amp. b: v g1-s =5v; v g2-s =v ds =0v - 50 na i g2-s gate cut-off current v g2-s =4v; v g1-s =v ds =0v - 20 na
2003 sep 30 5 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 0 v gg (v) 5 16 12 4 0 8 23 14 mgx430 i d (ma) (1) (2) (3) (4) (5) (6) fig.3 drain currents of mos-fet a and b as functions of v gg (see fig.4). (1) i d (b); r g1 = 120 k w . (2) i d (b); r g1 = 150 k w . (3) i d (b); r g1 = 180 k w . (4) i d (a); r g1 = 180 k w . (5) i d (a); r g1 = 150 k w . (6) i d (a); r g1 = 120 k w . handbook, halfpage mgx431 v gg r g1 d (a) s d (b) g1 (a) g2 g1 (b) fig.4 functional diagram v gg = 5 v: amplifier a is off; amplifier b is on. v gg = 0 v: amplifier a is on; amplifier b is off.
2003 sep 30 6 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 dynamic characteristics amplifier a common source; t amb =25 c; v g2-s =4v; v ds =5v; i d = 12 ma; note 1 notes 1. for the mos-fet not in use: v g1-s (b) = 0 v; v ds (b) = 0 v. 2. measured in fig.13 test circuit. symbol parameter conditions min. typ. max. unit ? y fs ? forward transfer admittance t j =25 c 263140ms c ig1-ss input capacitance at gate 1 f = 1 mhz - 1.8 2.3 pf c ig2-ss input capacitance at gate 2 f = 1 mhz - 3.3 - pf c oss output capacitance f = 1 mhz - 0.75 - pf c rss reverse transfer capacitance f = 1 mhz - 20 - ff g tr power gain f = 200 mhz; g s = 2 ms; b s =b s(opt) ; g l = 0.5 ms; b l =b l(opt) 31 35 39 db f = 400 mhz; g s = 2 ms; b s =b s(opt) ; g l = 1 ms; b l =b l(opt) 27 31 35 db f = 800 mhz; g s = 3.3 ms; b s =b s(opt) ; g l = 1 ms; b l =b l(opt) 22 26 30 db nf noise ?gure f = 10.7 mhz; g s = 20 ms; b s =0 - 4 - db f = 400 mhz; y s =y s(opt) - 1.1 1.7 db f = 800 mhz; y s =y s(opt) - 1.2 1.9 db x mod cross-modulation input level for k = 1% at 0 db agc; f w = 50 mhz; f unw = 60 mhz; note 2 90 -- db m v input level for k = 1% at 10 db agc; f w = 50 mhz; f unw = 60 mhz; note 2 - 90 - db m v input level for k = 1% at 40 db agc; f w = 50 mhz; f unw = 60 mhz; note 2 98 102 - db m v
2003 sep 30 7 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 graphs for amplifier a handbook, halfpage 02 0 5 10 15 20 0.4 0.8 1.2 1.6 v g1-s (v) i d (ma) mgx432 (7) (6) (5) (4) (1) (2) (3) fig.5 transfer characteristics; typical values; amplifier a. v ds (a) = 5 v; v g1-s (b) = v ds (b) = 0 v; t j =25 c. (1) v g2-s =4v. (2) v g2-s = 3.5 v. (3) v g2-s =3v. (4) v g2-s = 2.5 v. (5) v g2-s =2v. (6) v g2-s = 1.5 v. (7) v g2-s =1v. handbook, halfpage 010 24 0 8 16 2 v ds (v) i d (ma) 6 48 mgx433 (7) (6) (5) (4) (3) (2) (1) fig.6 output characteristics; typical values; amplifier a. v g2-s = 4 v; v g1-s (b)=v ds (b) = 0 v; t j =25 c. (1) v g1-s (a) = 1.4 v. (2) v g1-s (a) = 1.3 v. (3) v g1-s (a) = 1.2 v. (4) v g1-s (a) = 1.1 v. (5) v g1-s (a) = 1 v. (6) v g1-s (a) = 0.9 v. (7) v g1-s (a) = 0.8 v.
2003 sep 30 8 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 0 i d (ma) 420 40 30 10 0 20 81216 mgx434 y fs (ms) (5) (4) (3) (2) (1) fig.7 forward transfer admittance as a function of drain current; typical values; amplifier a. v ds (a) = 5 v; v g1-s (b) = v ds (b) = 0 v; t j =25 c. (1) v g2-s =4v. (2) v g2-s = 3.5 v. (3) v g2-s =3v. (4) v g2-s = 2.5 v. (5) v g2-s =2v. handbook, halfpage 01020 40 12 0 30 i d (b) ( m a) i d (a) (ma) 8 4 mgx435 fig.8 drain current as a function of internal g1 current (current in pin drain (b) if mos-fet (b) is switched off); typical values; amplifier a. v ds (a) = 5 v; v g2-s = 4 v; v ds (b) = 5 v; v g1-s (b) = 0 v; t j =25 c.
2003 sep 30 9 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 0 12 0 4 2 6 8 10 246 v gg = v ds (v) i d (ma) mgx436 (5) (4) (3) (2) (1) fig.9 drain current as a function of gate 2 and drain supply voltage; typical values; amplifier a. v ds (a) = 5 v; v g1-s (b) = 0 v; gate 1 (a) = open; t j =25 c. (1) v ds (b) = 5 v. (2) v ds (b) = 4.5 v. (3) v ds (b) = 4 v. (4) v ds (b) = 3.5 v. (5) v ds (b) = 3 v. handbook, halfpage 0 gain reduction (db) 60 120 110 90 80 100 20 40 mgx437 v unw (db m v) fig.10 unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier a. v ds (a)=v ds (b) = 5 v; v g1-s (b) = 0 v; f w = 50 mhz; f unw = 60 mhz; t amb =25 c; see fig.13.
2003 sep 30 10 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 012 4 0 60 3 v agc (v) gain reduction (db) 20 40 mgx438 fig.11 gain reduction as a function of agc voltage; typical values; amplifier a. v ds (a)=v ds (b) = 5 v; v g1-s (b) = 0 v; f = 50 mhz; see fig.13. handbook, halfpage 0 gain reduction (db) 60 16 12 4 0 8 20 40 mgx439 i d (ma) fig.12 drain current as a function of gain reduction; typical values; amplifier a. v ds (a)=v ds (b) = 5 v; v g1-s (b) = 0 v; f = 50 mhz; t amb =25 c; see fig.13. h andbook, full pagewidth l2 2.2 m h r g1 150 k w 10 k w r gen 50 w v i l1 2.2 m h mgx440 d (a) s d (b) g1 (a) g2 g1 (b) 4.7 nf 4.7 nf 4.7 nf 4.7 nf 4.7 nf BF1205 4.7 nf r l 50 w 50 w 50 w v ds (a) 5 v v ds (b) 5 v v gg 0 v v agc fig.13 cross-modulation test set-up for amplifier a.
2003 sep 30 11 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage mgx441 10 2 10 1 10 10 2 10 3 f (mhz) 10 - 2 10 - 1 y is (ms) g is b is fig.14 input admittance as a function of frequency; typical values; amplifier a. v ds (a) = 5 v; v g2-s (a) = 4 v; v ds (b)=v g1-s (b) = 0 v; i d (a) = 12 ma. handbook, halfpage mgx442 10 2 10 1 - 10 2 - 10 - 1 10 10 2 10 3 f (mhz) | y fs | (ms) j fs (deg) j fs | y fs | fig.15 forward transfer admittance and phase as a function of frequency; typical values; amplifier a. v ds (a) = 5 v; v g2-s (a) = 4 v; v ds (b)=v g1-s (b) = 0 v; i d (a) = 12 ma. handbook, halfpage mgx443 10 3 10 2 10 1 10 10 2 10 3 f (mhz) - 10 2 - 10 - 1 j rs (deg) - 10 3 | y rs | ( m s) j rs | y rs | fig.16 reverse transfer admittance and phase as a function of frequency; typical values; amplifier a. v ds (a) = 5 v; v g2-s (a) = 4 v; v ds (b)=v g1-s (b) = 0 v; i d (a) = 12 ma. handbook, halfpage mgx444 10 1 10 10 2 10 3 f (mhz) 10 - 2 10 - 1 y os (ms) g os b os fig.17 output admittance as a function of frequency; typical values; amplifier a. v ds (a) = 5 v; v g2-s (a) = 4 v; v ds (b)=v g1-s (b) = 0 v; i d (a) = 12 ma.
2003 sep 30 12 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 scattering parameters: ampli?er a v ds (a) = 5 v; v g2-s =4v; i d (a) = 12 ma; v ds (b) = 0 v; v g-1s (b) = 0 v; t amb =25 c noise data v ds (a) = 5 v; v g2-s =4v; i d (a) = 12 ma; v ds (b) = 0 v; v g-1s (b) = 0 v; t amb =25 c dynamic characteristics amplifier b common source; t amb =25 c; v g2-s =4v; v ds =5v; i d =12ma f (mhz) s 11 s 21 s 12 s 22 magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) 50 0.997 - 3.70 3.15 175.99 0.00067 86.39 0.992 - 1.38 100 0.995 - 7.37 3.15 171.92 0.00132 84.34 0.991 - 2.83 200 0.988 - 14.64 3.12 163.99 0.00262 79.71 0.990 - 5.62 300 0.976 - 21.85 3.09 156.06 0.00373 75.29 0.988 - 8.40 400 0.963 - 28.95 3.04 148.32 0.00471 71.43 0.985 - 11.15 500 0.944 - 35.98 2.99 140.52 0.00557 66.89 0.982 - 13.88 600 0.924 - 42.90 2.94 132.88 0.00624 63.52 0.978 - 16.65 700 0.900 - 49.77 2.87 125.30 0.00669 60.09 0.975 - 19.35 800 0.874 - 56.61 2.81 117.79 0.00701 59.58 0.972 - 22.08 900 0.846 - 63.18 2.73 110.29 0.00705 52.42 0.968 - 24.87 1000 0.817 - 69.84 2.65 102.91 0.00688 49.17 0.965 - 27.63 f (mhz) f min (db) gamma opt rn ( w ) (ratio) (deg) 400 1.1 0.719 16.16 31.18 800 1.2 0.628 32.7 29.74 symbol parameter conditions min. typ. max. unit ? y fs ? forward transfer admittance t j =25 c 263140ms c ig1-ss input capacitance at gate 1 f = 1 mhz - 2.0 2.5 pf c ig2-ss input capacitance at gate 2 f = 1 mhz - 3.3 - pf c oss output capacitance f = 1 mhz - 0.85 - pf c rss reverse transfer capacitance f = 1 mhz - 20 - ff g tr power gain f = 200 mhz; g s = 2 ms; b s =b s(opt) ; g l = 0.5 ms; b l =b l(opt) ; note 1 30 34 38 db f = 400 mhz; g s = 2 ms; b s =b s(opt) ; g l = 1 ms; b l =b l(opt) ; note 1 27 31 35 db f = 800 mhz; g s = 3.3 ms; b s =b s(opt) ; g l = 1 ms; b l =b l(opt) ; note 1 22 26 30 db nf noise ?gure f = 10.7 mhz; g s = 20 ms; b s =0 - 4 - db f = 400 mhz; y s =y s(opt) - 1.3 1.9 db f = 800 mhz; y s =y s(opt) - 1.4 2.1 db
2003 sep 30 13 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 notes 1. for the mos-fet not in use: v g1-s (a) = 0; v ds (a) = 0. 2. measured in test circuit fig.30. x mod cross-modulation input level for k = 1% at 0 db agc; f w = 50 mhz; f unw = 60 mhz; note 2 90 -- db m v input level for k = 1% at 10 db agc; f w = 50 mhz; f unw = 60 mhz; note 2 - 92 - db m v input level for k = 1% at 40 db agc; f w = 50 mhz; f unw = 60 mhz; note 2 100 105 - db m v symbol parameter conditions min. typ. max. unit graphs for amplifier b handbook, halfpage 02 0 5 10 15 20 0.4 0.8 1.2 1.6 v g1-s (v) i d (ma) mgx445 (6) (7) (5) (4) (1) (2) (3) fig.18 transfer characteristics; typical values; amplifier b. v ds (b) = 5 v; v ds (a)=v g1-s (a) = 0 v; t j =25 c. (1) v g2-s =4v. (2) v g2-s = 3.5 v. (3) v g2-s =3v. (4) v g2-s = 2.5 v. (5) v g2-s =2v. (6) v g2-s = 1.5 v. (7) v g2-s =1v. handbook, halfpage 010 24 0 8 16 2 v ds (v) i d (ma) 6 48 mgx446 (6) (7) (5) (4) (3) (2) (1) fig.19 output characteristics; typical values; amplifier b. v g2-s = 4 v; v ds (a) = v g1-s (a) = 0 v; t j =25 c. (1) v g1-s (b) = 1.4 v. (2) v g1-s (b) = 1.3 v. (3) v g1-s (b) = 1.2 v. (4) v g1-s (b) = 1.1 v. (5) v g1-s (b) = 1 v. (6) v g1-s (b) = 0.9 v. (7) v g1-s (b) = 0.8 v.
2003 sep 30 14 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 0 0.8 0.4 1.6 1.2 2 60 20 0 40 mgx447 v g1-s (v) i g1 ( m a) (7) (5) (4) (6) (3) (2) (1) fig.20 gate 1 current as a function of gate 1 voltage; typical values; amplifier b. v ds (b) = 5 v; v ds (a)=v g1-s (a) = 0 v; t j =25 c. (1) v g2-s =4v. (2) v g2-s = 3.5 v. (3) v g2-s =3v. (4) v g2-s = 2.5 v. (5) v g2-s =2v. (6) v g2-s = 1.5 v. (7) v g2-s =1v. handbook, halfpage 0 i d (ma) 420 40 30 10 0 20 81216 mgx448 y fs (ms) (5) (4) (3) (2) (1) fig.21 forward transfer admittance as a function of drain current; typical values; amplifier b. v ds (b) = 5 v; v ds (a)=v g1-s (a) = 0 v; t j =25 c. (1) v g2-s =4v. (2) v g2-s = 3.5 v. (3) v g2-s =3v. (4) v g2-s = 2.5 v. (5) v g2-s =2v.
2003 sep 30 15 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 050 20 0 4 8 12 16 10 20 30 40 i g1 ( m a) i d (ma) mgx449 fig.22 drain current as a function of gate 1 current; typical values; amplifier b. v ds (b) = 5 v; v g2-s = 4 v; v ds (a)=v g1-s (a) = 0 v; t j =25 c. handbook, halfpage 0 v gg (v) 15 16 12 4 0 8 23 4 mgx450 i d (ma) fig.23 drain current as a function of gate 1 supply voltage (v gg ); typical values; amplifier b. v ds (b) = 5 v; v g2-s = 4 v; v ds (a)=v g1-s (a) = 0 v; t j =25 c; r g1 (b) = 150 k w (connected to v gg ); see fig.4.
2003 sep 30 16 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 0246 v gg = v ds (v) i d (ma) 20 0 16 12 8 4 mgx451 (6) (7) (8) (5) (4) (3) (2) (1) fig.24 drain current as a function of gate 1 (v gg ) and drain supply voltage; typical values; amplifier b. v g2-s = 4 v; v ds (a) = v g1-s (a) = 0 v; t j =25 c; r g1 (b) = 150 k w (connected to v gg ); see fig.4. (1) r g1 (b)=68k w . (2) r g1 (b)=82k w . (3) r g1 (b) = 100 k w . (4) r g1 (b) = 120 k w . (5) r g1 (b) = 150 k w . (6) r g1 (b) = 180 k w . (7) r g1 (b) = 220 k w . (8) r g1 (b) = 270 k w . handbook, halfpage 0246 16 12 4 0 8 mgx452 v g2-s (v) i d (ma) (5) (4) (3) (2) (1) fig.25 drain current as a function of gate 2 voltage; typical values; amplifier b. v ds (b) = 5 v; v ds (a)=v g1-s (a) = 0 v; t j =25 c; r g1 (b) = 150 k w (connected to v gg ); see fig.4. (1) v gg = 5.0 v. (2) v gg = 4.5 v. (3) v gg = 4.0 v. (4) v gg = 3.5 v. (5) v gg = 3.0 v.
2003 sep 30 17 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 0246 30 10 0 20 mgx453 v g2-s (v) i g1 ( m a) (5) (4) (3) (2) (1) fig.26 gate 1 current as a function of gate 2 voltage; typical values; amplifier b. v ds (b) = 5 v; v ds (a)=v g1-s (a) = 0 v; t j =25 c; r g1 (b) = 150 k w (connected to v gg ); see fig.4. (1) v gg = 5.0 v. (2) v gg = 4.5 v. (3) v gg = 4.0 v. (4) v gg = 3.5 v. (5) v gg = 3.0 v. handbook, halfpage 0 gain reduction (db) 60 120 110 90 80 100 20 40 mgx454 v unw (db m v) fig.27 unwanted voltage for 1% cross-modulation as a function of gain reduction; typical values; amplifier b. v ds (b) = 5 v; v gg = 5 v; v ds (a)=v g1-s (a) = 0 v; r g1 (b) = 150 k w (connected to v gg ); f w = 50 mhz; f unw = 60 mhz; t amb =25 c; see fig.30.
2003 sep 30 18 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage 012 4 0 60 3 v agc (v) gain reduction (db) 20 40 mgx455 fig.28 typical gain reduction as a function of agc voltage; amplifier b. v ds (b) = 5 v; v gg = 5 v; v ds (a)=v g1-s (a) = 0 v; r g1 (b) = 150 k w (connected to v gg ); f = 50 mhz; t amb =25 c; see fig.30. handbook, halfpage 0 gain reduction (db) 60 16 12 4 0 8 20 40 mgx456 i d (ma) fig.29 drain current as a function of gain reduction; typical values; amplifier b. v ds (b) = 5 v; v gg = 5 v; v ds (a)=v g1-s (a) = 0 v; r g1 (b) = 150 k w (connected to v gg ); f = 50 mhz; t amb =25 c; see fig.30.
2003 sep 30 19 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, full pagewidth l2 2.2 m h r g1 150 k w 10 k w l1 2.2 m h mdb813 d (a) s d (b) g1 (a) g2 g1 (b) 4.7 nf 4.7 nf 4.7 nf 4.7 nf BF1205 4.7 nf r l 50 w 50 w r gen 50 w v i 50 w v ds (a) 5 v v ds (b) 5 v v gg 5 v v agc fig.30 cross-modulation test set-up for amplifier b. handbook, halfpage mgx457 10 2 10 1 10 10 2 10 3 f (mhz) 10 - 1 y is (ms) g is b is fig.31 input admittance as a function of frequency; typical values; amplifier b. v ds (b) = 5 v; v g2-s = 4 v; v ds (a)=v g1-s (a) = 0 v; i d (b)= 12 ma. handbook, halfpage mgx458 10 2 10 1 - 10 2 - 10 - 1 10 10 2 10 3 f (mhz) | y fs | (ms) j fs (deg) j fs | y fs | fig.32 forward transfer admittance and phase as a function of frequency; typical values; amplifier b. v ds (b) = 5 v; v g2-s = 4 v; v ds (a)=v g1-s (a) = 0 v; i d (b) = 12 ma.
2003 sep 30 20 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 handbook, halfpage mgx459 10 3 10 2 10 1 10 10 2 10 3 f (mhz) - 10 2 - 10 - 1 j rs (deg) - 10 3 | y rs | ( m s) | y rs | j rs fig.33 reverse transfer admittance and phase as a function of frequency; typical values; amplifier b. v ds (b) = 5 v; v g2-s = 4 v; v ds (a)=v g1-s (a) = 0 v; i d (b) = 12 ma. handbook, halfpage mgx460 10 1 10 10 2 10 3 f (mhz) 10 - 2 10 - 1 y os (ms) g os b os fig.34 output admittance as a function of frequency; typical values; amplifier b. v ds (b) = 5 v; v g2-s = 4 v; v ds (a)=v g1-s (a) = 0 v; i d (b) = 12 ma.
2003 sep 30 21 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 scattering parameters: ampli?er b v ds (b) = 5 v; v g2-s =4v; i d (b) = 12 ma; v ds (a) = 0 v; v g1-s (a) = 0 v; t amb =25 c noise data v ds (b) = 5 v; v g2-s =4v; i d (b) = 12 ma; v ds (a) = 0 v; v g1-s (a) = 0 v; t amb =25 c f (mhz) s 11 s 21 s 12 s 22 magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) magnitude (ratio) angle (deg) 50 0.987 - 3.76 3.12 175.87 0.00071 85.43 0.991 - 1.56 100 0.985 - 7.38 3.11 171.77 0.00136 86.06 0.989 - 3.11 200 0.978 - 14.63 3.09 163.72 0.00272 84.25 0.988 - 6.16 300 0.968 - 21.82 3.06 155.67 0.00396 82.63 0.986 - 9.17 400 0.956 - 28.92 3.01 147.79 0.00509 81.35 0.983 - 12.17 500 0.941 - 35.99 2.95 139.86 0.00616 79.46 0.973 - 15.16 600 0.924 - 42.93 2.89 132.06 0.00710 78.57 0.975 - 18.15 700 0.905 - 49.89 2.83 124.31 0.00791 77.88 0.972 - 21.07 800 0.884 - 56.57 2.75 116.69 0.00848 76.72 0.968 - 24.08 900 0.861 - 63.36 2.67 108.97 0.00900 76.55 0.964 - 27.03 1000 0.837 - 70.05 2.59 101.39 0.00941 76.67 0.959 - 30.02 f (mhz) f min (db) f min (db) r n ( w ) (ratio) (deg) 400 1.3 0.662 16.76 31.55 800 1.4 0.578 33.97 30.53
2003 sep 30 22 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 package outline references outline version european projection issue date iec jedec eiaj sot363 sc-88 wb m b p d e 1 e pin 1 index a a 1 l p q detail x h e e v m a a b y 0 1 2 mm scale c x 13 2 4 5 6 plastic surface mounted package; 6 leads sot363 unit a 1 max b p cd e e 1 h e l p qy w v mm 0.1 0.30 0.20 2.2 1.8 0.25 0.10 1.35 1.15 0.65 e 1.3 2.2 2.0 0.2 0.1 0.2 dimensions (mm are the original dimensions) 0.45 0.15 0.25 0.15 a 1.1 0.8 97-02-28
2003 sep 30 23 philips semiconductors product speci?cation dual n-channel dual gate mos-fet BF1205 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r77/01/pp 24 date of release: 2003 sep 30 document order number: 9397 750 11784

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